Xilinx Memory Interface Generator (MIG) による DDR2 SDRAM のアクセス のバックアップ(No.5)

更新


公開メモ

概要

以下の内容はまだ試行錯誤中のもので、間違っている可能性が多分にあります。

紛らわしい記事ですみません。

一応、Xilinx FPGA から DDR や DDR2、DDR3 といった高速メモリにアクセスすることを目的に、

  1. Memory Interface Generator (MIG) というソフトを使ってIPコアを生成する方法
  2. 生成したIPコア経由で Spartan 3A DSP から DDR2 メモリにアクセスする方法

をまとめる予定です。

詳細としては、

Core name: Xilinx MIG
Version: 3.3
Release Date: December 2, 2009

を使って、

Spartan 3A DSP 1800 Starter Platform

用のコアを作成し、その使い方について調べたものです。

入出力ポートを指定してコアを生成する

まずは MIG を使ってIPコアを生成する方法についてなのですが、 一見簡単そうに見えて、思ったよりも難しかったです。

というか、まだうまく行ってるのかどうか自信が持てません。

  1. Xilinx の Reference Board 用にコアを作る方法
  2. FPGA のどのピンを、メモリのどのピンと結線したらよいかを MIG に決めてもらう方法

は簡単に分かったのですが、Starter Platform を買った場合のように PCBがすでにできていて、MIG が想定するのと異なるピン配置で FPGA がメモリと接続されている場合に使えるコアを どのように生成すればよいかが分かりにくかったので、 以下に手順をまとめておきます。

情報源

基本は MIG の User Guid (MIG を起動した画面の左下のボタン : ug086) の

  • Chapter 1 : Using MIG
    • MIG User Interface
      • MIG Output Options
        Verify UCF and Update Design and UCF

に沿っていきます。

MIG の2ページ目で [Create Design] を指定する

MIG を起動した際の一番目の選択肢です。

mig2.png

最終的には Verify UCF and Update Design and UCF を使うのですが、 始めは .ucf に指定するための信号名が分からないので、 ここでは一旦 [Create Design] を選びます。

メモリの仕様に合わせてオプションを選択する

Spartan 3A DSP 1800 Starter Platform 用に次のように指定しました。

自信のないところもあるのですが、、、

うまく行かなかったらまた考えます。

Memory SelectionDDR2 SDRAM
Frequency8000 ps = 125MHz
Write Pipe Stages4
Memory TypeComponents
Memory PartMT47H32M16-3
Data Width32
Data MaskUncheck
Burst Length4
Burst Typesequential
Output Drive StrengthFullstrength
RTT(nominal)-ODT75ohms ?
DQS# EnableEnable
Use DCMUncheck
Class for Address and ControlClass II
Class for DataClass II
Debug Signals for Memory ControllerDisable

Available/Reserved ピンは指定しない

つぎにピン配置を決めるのですが・・・

[Create Design] モードというのは、新たにPCBを起こす際に MIG にお勧めの結線方法を提案してもらうというモードなので、 このモードではどんなに頑張っても1つ1つのピン配置を こちらから指定することはできません。

メモリとの接続に使ってもよいピンを MIG に教えると、 MIG がピン配置を勝手に決め、その配置でコアを生成するという 話になっています。

デフォルトでは全てのピンが Available Pins に入っていて、 MIG はその中から適当なピンを選んでコアを生成します。

もちろんそれでは困るのですが、 どうしようもないので後で直すことにして、 ここではそのままにしておきます。

ちなみに、このページの [Read UCF File] は興味を引くボタンなのですが、、、

他の用途に使っているためにメモリとの配線に使えないピンを Reserved Pins として登録するためのもので、メモリとの配線方法を指定するためのものでは無いので、 残念ながら押しても役に立ちません。

Bank は(念のため)本来のピン配置と同じものを選んでおく

MIG は上述の Available Pins から適当なピンを選んで信号線を割り当てますが、 このページでは信号線の種類毎に、使う Bank を指定することができます。

mig4.png

目的のボードに合わせてバンクを選択すればよいのだと思います。

コアを生成する

どんどんページをめくって、最後にライセンスを承諾するとコアが生成されます。

ピンを指定するための ucf ファイルを作る

ここからいよいよピン配置を指定する段階です。

私の場合 ddr2mi という名前でコアを作ったので、 できたコアは以下のディレクトリにありました。

(project folder)/ipcore_dir/ddr2mi/user_design

このフォルダの par/ddr2mi.ucf に、MIG が適当に決定したピン配置と、 そのピン配置に最適化された回路を生成するための ucf ファイルが作成されています。

このファイルから #bank というコメントが付いている行を抜き出すと、 ピン配置を指定している行だけを抽出できます。

unix ライクなコンソールが使えれば、

LANG:console
$ grep -i "#bank" ipcore_dir/ddr2mi/user_design/par/ddr2mi.ucf | sort > ddr2mi_pins.ucf

とすることで、

ddr2mi_pins.ucf

NET "cntrl0_ddr2_a[0]" LOC = "J21" ;     #bank 1
NET "cntrl0_ddr2_a[10]" LOC = "B2" ;     #bank 3
NET "cntrl0_ddr2_a[11]" LOC = "H7" ;     #bank 3
NET "cntrl0_ddr2_a[12]" LOC = "G6" ;     #bank 3
...

NET "cntrl0_ddr2_dqs_n[6]" LOC = "J4";     #bank 3
NET "cntrl0_ddr2_dqs_n[7]" LOC = "J6";     #bank 3
NET "cntrl0_rst_dqs_div_in" LOC = "G4";     #bank 3
NET "cntrl0_rst_dqs_div_out" LOC = "F5";     #bank 3

のようなファイルができます。

これを自分のボードに合わせて編集し、正しいピンを指定します。

ucf ファイルを元にコアのピン配置を変更する

上記の手順でピン配置だけを変更しても、FPGA 内部のプリミティブ配置は MIG が最初に提案したピン配置に最適化されているのでそのままでは動きません。

そこで、もう一度 MIG を起動してコアを作り直します。

Design ペインの Hierarchy で先ほど生成した ddr2mi をダブルクリックして MIG を起動します。

mig6.png

今度は [Verify UCF and Update Design and UCF] を選択し、
Load Prj File に ipcore_dir/ddr2mi/user_design/mig.prj
Load UCF File に ddr2mi_pins.ucf (ピンを指定するための自分で作ったファイル)
を指定します。

Next を連打して、もう一度ライセンス条項を許諾すると、 指定したピン配置でコアを生成できます。

正しいピン配置になっているかどうか確認する

LANG:console
$ grep -i "#bank" ipcore_dir/ddr2mi/user_design/par/ddr2mi.ucf | sort > ddr2mi_pins.ucf

としてみると、指定した通りのピン配置でコアが生成されていると思います。

オリジナルの構成と比べてみる

LANG:console
$ grep -i "#bank" ddr2mi_original.ucf | sed -e "s/#bank.*//i" -e "s/\r//" | sort > original-pins.txt
$ grep -i "#bank" ddr2mi.ucf | sed -e "s/#bank.*//i" -e "s/\r//" | sort > custom-pins.txt
$ paste *pins.txt > compare.txt

として、形式を整えたものが次の表です。

ピン名称カスタムオリジナル
cntrl0_ddr2_a[0]J5M4
cntrl0_ddr2_a[1]M9M6
cntrl0_ddr2_a[2]M10M5
cntrl0_ddr2_a[3]K4N4
cntrl0_ddr2_a[4]K5N5
cntrl0_ddr2_a[5]K2N2
cntrl0_ddr2_a[6]K3N1
cntrl0_ddr2_a[7]L3N7
cntrl0_ddr2_a[8]L4N6
cntrl0_ddr2_a[9]M7P2
cntrl0_ddr2_a[10]M8P1
cntrl0_ddr2_a[11]M3W6
cntrl0_ddr2_a[12]M4W7
cntrl0_ddr2_ba[0]K6M8
cntrl0_ddr2_ba[1]J4M3
cntrl0_ddr2_cas_nL10K3
cntrl0_ddr2_ck[0]N1AD1
cntrl0_ddr2_ck[1]N5AC2
cntrl0_ddr2_ck_n[0]N2AD2
cntrl0_ddr2_ck_n[1]N4AC3
cntrl0_ddr2_ckeL7M7
cntrl0_ddr2_cs_nH2L4
cntrl0_ddr2_odtG3K5
cntrl0_ddr2_ras_nH1L3
cntrl0_ddr2_we_nL9K2
reset_in_nG8G8
cntrl0_ddr2_dq[0]U9U9
cntrl0_ddr2_dq[1]V8V8
cntrl0_ddr2_dq[2]AB1AB1
cntrl0_ddr2_dq[3]AC1AC1
cntrl0_ddr2_dq[4]Y5Y5
cntrl0_ddr2_dq[5]Y6Y6
cntrl0_ddr2_dq[6]U7U7
cntrl0_ddr2_dq[7]U8U8
cntrl0_ddr2_dq[8]AA2AA2
cntrl0_ddr2_dq[9]AA3AA3
cntrl0_ddr2_dq[10]Y1Y1
cntrl0_ddr2_dq[11]Y2Y2
cntrl0_ddr2_dq[12]T7T7
cntrl0_ddr2_dq[13]U6U6
cntrl0_ddr2_dq[14]U5U5
cntrl0_ddr2_dq[15]V5V5
cntrl0_ddr2_dq[16]R8V1
cntrl0_ddr2_dq[17]R7R7
cntrl0_ddr2_dq[18]U1R8
cntrl0_ddr2_dq[19]U2U2
cntrl0_ddr2_dq[20]P8P8
cntrl0_ddr2_dq[21]P9P9
cntrl0_ddr2_dq[22]R5R5
cntrl0_ddr2_dq[23]R6R6
cntrl0_ddr2_dq[24]P7P7
cntrl0_ddr2_dq[25]P6P6
cntrl0_ddr2_dq[26]T3T3
cntrl0_ddr2_dq[27]T4T4
cntrl0_ddr2_dq[28]N9N9
cntrl0_ddr2_dq[29]P10R2
cntrl0_ddr2_dq[30]P4P4
cntrl0_ddr2_dq[31]P3P3
cntrl0_ddr2_dqs[0]V7V7
cntrl0_ddr2_dqs[1]W3W3
cntrl0_ddr2_dqs[2]T5T5
cntrl0_ddr2_dqs[3]R3R3
cntrl0_ddr2_dqs_n[0]V6V6
cntrl0_ddr2_dqs_n[1]W4W4
cntrl0_ddr2_dqs_n[2]U4U4
cntrl0_ddr2_dqs_n[3]R4R4
cntrl0_rst_dqs_div_inT9T9
cntrl0_rst_dqs_div_outT10T10

黄色のピンがオリジナルと異なる部分です。

データ部分などはほぼぴったり同じなのですね。

気になる点

カスタム .ucf を喰わせた後、Verification Report のところでかなりの数の Warning が出ました。

                      Verification Report                          

/*******************************************************/
/*                   Controller 0                           
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Mask bits ...
Checking pins allocated to Clock bits ... 
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
WARNING: LUT delay location constraint for dqs_delayed column of dqs[3] are missing..
WARNING: LUT delay BEL constraint constraints of dqs[3] are missing..
WARNING: Fifo write address and write enable constraints of dqs[3] are missing..
WARNING: Slice location constraints of dq[31] are missing..
WARNING: Slice location constraints of dq[30] are missing..
WARNING: Slice location constraints of dq[29] are missing..
WARNING: Slice location constraints of dq[28] are missing..
WARNING: Slice location constraints of dq[27] are missing..
WARNING: Slice location constraints of dq[26] are missing..
WARNING: Slice location constraints of dq[25] are missing..
WARNING: Slice location constraints of dq[24] are missing..
WARNING: LUT delay location constraint for dqs_delayed column of dqs[2] are missing..
WARNING: LUT delay BEL constraint constraints of dqs[2] are missing..
WARNING: Fifo write address and write enable constraints of dqs[2] are missing..
WARNING: Slice location constraints of dq[23] are missing..
WARNING: Slice location constraints of dq[22] are missing..
WARNING: Slice location constraints of dq[21] are missing..
WARNING: Slice location constraints of dq[20] are missing..
WARNING: Slice location constraints of dq[19] are missing..
WARNING: Slice location constraints of dq[18] are missing..
WARNING: Slice location constraints of dq[17] are missing..
WARNING: Slice location constraints of dq[16] are missing..
WARNING: LUT delay location constraint for dqs_delayed column of dqs[1] are missing..
WARNING: LUT delay BEL constraint constraints of dqs[1] are missing..
WARNING: Fifo write address and write enable constraints of dqs[1] are missing..
WARNING: Slice location constraints of dq[15] are missing..
WARNING: Slice location constraints of dq[14] are missing..
WARNING: Slice location constraints of dq[13] are missing..
WARNING: Slice location constraints of dq[12] are missing..
WARNING: Slice location constraints of dq[11] are missing..
WARNING: Slice location constraints of dq[10] are missing..
WARNING: Slice location constraints of dq[9] are missing..
WARNING: Slice location constraints of dq[8] are missing..
WARNING: LUT delay location constraint for dqs_delayed column of dqs[0] are missing..
WARNING: LUT delay BEL constraint constraints of dqs[0] are missing..
WARNING: Fifo write address and write enable constraints of dqs[0] are missing..
WARNING: Slice location constraints of dq[7] are missing..
WARNING: Slice location constraints of dq[6] are missing..
WARNING: Slice location constraints of dq[5] are missing..
WARNING: Slice location constraints of dq[4] are missing..
WARNING: Slice location constraints of dq[3] are missing..
WARNING: Slice location constraints of dq[2] are missing..
WARNING: Slice location constraints of dq[1] are missing..
WARNING: Slice location constraints of dq[0] are missing..
WARNING: Some of the RLOC/U_SET Constraints of the LUT delay calibration circuit are missing.
WARNING: Some of the BEL constraints of the LUT delay calibration circuit are missing.
WARNING: Slice location constraint for delayed rst_dqs_div_out signal is missing.

Verification completed. Found the following warnings.
Number of warnings in the input UCF = 47.
Verification Successful.
All signals in the UCF were allocated correctly.

与えた .ucf ファイルにはピン配置制約以外書いていないので、それを検出しているものであって、 できあがった .ucf ファイルはこれら Warning の点を修正したものであると考えていたのですが、 試しに再生成された .ucf ファイルを指定して Verify UCF and Update Design and UCF してみたところ、、、

                      Verification Report                          

/*******************************************************/
/*                   Controller 0                           
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Clock bits ... 
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five-slice_x3y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four-slice_x2y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one-slice_x2y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six-slice_x3y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three-slice_x2y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two-slice_x2y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five-slice_x1y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four-slice_x0y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one-slice_x0y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six-slice_x1y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three-slice_x0y78" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two-slice_x0y79" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four-f" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one-f" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four-f" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one-f" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two-g" for dqs_delayed column of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit0-slice_x1y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit1-slice_x1y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit2-slice_x1y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit3-slice_x1y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit0-slice_x3y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit1-slice_x3y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit2-slice_x3y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit3-slice_x3y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[3].fifo_0_wr_en_inst-slice_x1y77" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[3].fifo_1_wr_en_inst-slice_x3y77" for Fifo write address or write enable of dqs[3] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit7-slice_x2y86" allocated for dq[31] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit7-slice_x2y87" allocated for dq[31] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit6-slice_x0y86" allocated for dq[30] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit6-slice_x0y87" allocated for dq[30] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit5-slice_x2y84" allocated for dq[29] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit5-slice_x2y85" allocated for dq[29] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit4-slice_x0y84" allocated for dq[28] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit4-slice_x0y85" allocated for dq[28] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit3-slice_x2y76" allocated for dq[27] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit3-slice_x2y77" allocated for dq[27] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit2-slice_x0y76" allocated for dq[26] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit2-slice_x0y77" allocated for dq[26] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit1-slice_x2y74" allocated for dq[25] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit1-slice_x2y75" allocated for dq[25] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit0-slice_x0y74" allocated for dq[24] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit0-slice_x0y75" allocated for dq[24] is invalid.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five-slice_x3y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four-slice_x2y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one-slice_x2y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six-slice_x3y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three-slice_x2y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two-slice_x2y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five-slice_x1y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four-slice_x0y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one-slice_x0y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six-slice_x1y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three-slice_x0y66" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two-slice_x0y67" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four-f" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one-f" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four-f" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one-f" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two-g" for dqs_delayed column of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit0-slice_x1y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit1-slice_x1y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit2-slice_x1y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit3-slice_x1y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit0-slice_x3y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit1-slice_x3y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit2-slice_x3y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit3-slice_x3y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[2].fifo_0_wr_en_inst-slice_x1y65" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[2].fifo_1_wr_en_inst-slice_x3y65" for Fifo write address or write enable of dqs[2] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit7-slice_x2y70" allocated for dq[23] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit7-slice_x2y71" allocated for dq[23] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit6-slice_x0y70" allocated for dq[22] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit6-slice_x0y71" allocated for dq[22] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit5-slice_x2y68" allocated for dq[21] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit5-slice_x2y69" allocated for dq[21] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit4-slice_x0y68" allocated for dq[20] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit4-slice_x0y69" allocated for dq[20] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit3-slice_x2y60" allocated for dq[19] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit3-slice_x2y61" allocated for dq[19] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit2-slice_x0y60" allocated for dq[18] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit2-slice_x0y61" allocated for dq[18] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit1-slice_x2y58" allocated for dq[17] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit1-slice_x2y59" allocated for dq[17] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit0-slice_x0y58" allocated for dq[16] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit0-slice_x0y59" allocated for dq[16] is invalid.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-slice_x3y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-slice_x2y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-slice_x2y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-slice_x3y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-slice_x2y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-slice_x2y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-slice_x1y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-slice_x0y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-slice_x0y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-slice_x1y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-slice_x0y44" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-slice_x0y45" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0-slice_x1y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1-slice_x1y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2-slice_x1y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3-slice_x1y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0-slice_x3y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1-slice_x3y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2-slice_x3y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3-slice_x3y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst-slice_x1y43" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst-slice_x3y43" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7-slice_x2y50" allocated for dq[15] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7-slice_x2y51" allocated for dq[15] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6-slice_x0y50" allocated for dq[14] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6-slice_x0y51" allocated for dq[14] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5-slice_x2y46" allocated for dq[13] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5-slice_x2y47" allocated for dq[13] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4-slice_x0y46" allocated for dq[12] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4-slice_x0y47" allocated for dq[12] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3-slice_x2y42" allocated for dq[11] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3-slice_x2y43" allocated for dq[11] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2-slice_x0y42" allocated for dq[10] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2-slice_x0y43" allocated for dq[10] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1-slice_x2y38" allocated for dq[9] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1-slice_x2y39" allocated for dq[9] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0-slice_x0y38" allocated for dq[8] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0-slice_x0y39" allocated for dq[8] is invalid.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-slice_x3y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-slice_x2y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-slice_x2y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-slice_x3y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-slice_x2y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-slice_x2y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-slice_x1y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-slice_x0y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-slice_x0y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-slice_x1y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-slice_x0y30" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-slice_x0y31" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0-slice_x1y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1-slice_x1y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2-slice_x1y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3-slice_x1y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0-slice_x3y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1-slice_x3y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2-slice_x3y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3-slice_x3y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst-slice_x1y29" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst-slice_x3y29" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7-slice_x2y36" allocated for dq[7] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7-slice_x2y37" allocated for dq[7] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6-slice_x0y36" allocated for dq[6] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6-slice_x0y37" allocated for dq[6] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5-slice_x2y34" allocated for dq[5] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5-slice_x2y35" allocated for dq[5] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4-slice_x0y34" allocated for dq[4] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4-slice_x0y35" allocated for dq[4] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3-slice_x2y28" allocated for dq[3] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3-slice_x2y29" allocated for dq[3] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2-slice_x0y28" allocated for dq[2] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2-slice_x0y29" allocated for dq[2] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1-slice_x2y26" allocated for dq[1] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1-slice_x2y27" allocated for dq[1] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0-slice_x0y26" allocated for dq[0] is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0-slice_x0y27" allocated for dq[0] is invalid.
WARNING: The signal cntrl0_led_error_output1 is missing or allocated to invalid I/O.
WARNING: The signal cntrl0_data_valid_out is missing or allocated to invalid I/O.
WARNING: The signal cntrl0_init_done is missing or allocated to invalid I/O.
WARNING: Slice location constraint for delayed rst_dqs_div_out signal is not correct.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-slice_x1y52" for delayed rst_dqs_div_in signal is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-slice_x1y52" for delayed rst_dqs_div_in signal is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-slice_x0y53" for delayed rst_dqs_div_in signal is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-slice_x1y53" for delayed rst_dqs_div_in signal is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-slice_x0y53" for delayed rst_dqs_div_in signal is invalid.
WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-slice_x0y52" for delayed rst_dqs_div_in signal is invalid.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-g" for delayed rst_dqs_div_in signal is not correct.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-f" for delayed rst_dqs_div_in signal is not correct.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-f" for delayed rst_dqs_div_in signal is not correct.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-g" for delayed rst_dqs_div_in signal is not correct.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-g" for delayed rst_dqs_div_in signal is not correct.
WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-g" for delayed rst_dqs_div_in signal is not correct.

Verification completed. Found the following warnings.
Number of warnings in the input UCF = 216.
Verification Successful.
All signals in the UCF were allocated correctly.

むしろ WARNING が大幅に増えていました(泣

対照的に、ピン配置を指定せず、Create Design で作った .ucf ファイルをそのまま指定して Verify UCF and Update Design and UCF すると、以下のように Warning は1つも出ません。

                      Verification Report                          

Reading design libraries of xc3sd1800a-fg676... successful !

/*******************************************************/
/*                   Controller 0                           
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Clock bits ... 
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
Verification Successful.
All signals in the UCF were allocated correctly.

うまくいってない!

ここまでやっておいて何ですが、上記手順ではうまく .ucf を再生成できていないようです。

うまく行きました

で、ものは試し、と、上記のように大量の Warning が出たのをめげずに 進んで、もう一度コアを作り直し、そうしてできた .ucf ファイルを Verify UCF and Update Design and UCF に与えたところ、

                      Verification Report                          

/*******************************************************/
/*                   Controller 0                           
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Clock bits ... 
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
Verification Successful.
All signals in the UCF were allocated correctly.

のように、WARNING が出なくなりました。

もともと、「ピン配置だけを抜き出して書き換えた」 .ucf ファイルを作ったのが間違いで、 オリジナルの .ucf ファイルを「ピン配置部分だけを書き換えた」.ucf ファイルを与えて Verify UCF and Update Design and UCF すれば良かったのかもしれません。

とりあえず、これで先に進めます。

MIG が生成したコアを使って Spartan 3A DSP から DDR2 メモリにアクセスする

まだ準備段階です。

Spartan 3A DSP 1800 Starter Platform には Micron の 16bit 幅で 512Mbit の DDR2 SDRAM である MT47H32M16BM-3 が 2つ載っていて、合計で 32bit 幅 1024Mbit の構成になっています。

DDR2 メモリには最低動作周波数が規定されていて、このチップでは 125MHz となっているため、 Spartan 3 ではちょっと厳しめですが、この周波数でデータの受け渡しをしなければなりません。

また、MIG のインターフェースは元クロックと 90度 および 180度 位相の異なるクロックを利用してデータの受け渡しをするように設計されていて、 そのあたりもちょっとハードルが高いです。

とはいえ、考え方が分かってしまえば、高速回路設計の勉強にもなっていい感じです。

(まだ実機で動かせるところまで進んでいませんが)

メモリの構成

合計 1024Mbit で 32bit 幅なので、アドレス空間は 0x0000000 - 0x1ffffff の 25ビット幅になります。

ddr2mi_parameter_0.v を見ると

LANG:verilog
`define   ROW_ADDRESS                              13
`define   COLUMN_ADDRESS                           10
`define   BANK_ADDRESS                             2

となっていて、合計値は正しく 25 ビットになっていました。

モードレジスタの値

ddr2mi_parameter_0.v によれば、

LOAD_MODE_REGISTER                       13'b0010100110010

となっていますので、これをメモリのデータシートと突き合わせると、

mode_reg.png

項目意味
Mode Register Definition00Mode register (MR)
PD Mode0Fast exit
Write Recovery0103
DLL Reset1Yes
Test Mode0Normal Mode
CAS#0
CAS Latency (CL)113
Burst Type0Sequential
Burst Length0104

という設定であることが分かります。

メモ

  • Invalid property "SYN_USEIOFF 1" というワーニングは XST が Synplify 用の制約である SYN_USEIOFF を認識できないために出るものなので、無視して良さそうです。

コメント





Counter: 55119 (from 2010/06/03), today: 6, yesterday: 0