Xilinx Memory Interface Generator (MIG) による DDR2 SDRAM のアクセスのバックアップソース(No.7)

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#contents

* 概要 [#v3e85f93]

以下の内容はまだ試行錯誤中のもので、間違っている可能性が多分にあります。

紛らわしい記事ですみません。

一応、Xilinx FPGA から DDR や DDR2、DDR3 といった高速メモリにアクセスすることを目的に、
+ Memory Interface Generator (MIG) というソフトを使ってＩＰコアを生成する方法
+ 生成したＩＰコア経由で Spartan 3A DSP から DDR2 メモリにアクセスする方法

をまとめる予定です。

詳細としては、

 Core name: Xilinx MIG
 Version: 3.3
 Release Date: December 2, 2009

を使って、

 Spartan 3A DSP 1800 Starter Platform

用のコアを作成し、その使い方について調べたものです。

* 入出力ポートを指定してコアを生成する [#c78446c5]

まずは MIG を使ってＩＰコアを生成する方法についてなのですが、
一見簡単そうに見えて、思ったよりも難しかったです。

というか、まだうまく行ってるのかどうか自信が持てません。

+ Xilinx の Reference Board 用にコアを作る方法
+ FPGA のどのピンを、メモリのどのピンと結線したらよいかを MIG に決めてもらう方法

は簡単に分かったのですが、Starter Platform を買った場合のように
ＰＣＢがすでにできていて、MIG が想定するのと異なるピン配置で
FPGA がメモリと接続されている場合に使えるコアを
どのように生成すればよいかが分かりにくかったので、
以下に手順をまとめておきます。

** 情報源 [#d4aa8543]

基本は MIG の User Guid (MIG を起動した画面の左下のボタン : ug086）
の 
- Chapter 1 : Using MIG
-- MIG User Interface
--- MIG Output Options~
Verify UCF and Update Design and UCF

に沿っていきます。

** MIG の２ページ目で [Create Design] を指定する [#r9f457ed]

MIG を起動した際の一番目の選択肢です。

&attachref(mig2.png,,50%);

最終的には Verify UCF and Update Design and UCF を使うのですが、
始めは .ucf に指定するための信号名が分からないので、
ここでは一旦 [Create Design] を選びます。

** メモリの仕様に合わせてオプションを選択する [#me3ee50b]

Spartan 3A DSP 1800 Starter Platform 用に次のように指定しました。

自信のないところもあるのですが、、、

うまく行かなかったらまた考えます。

|Memory Selection|DDR2 SDRAM|
|>||
|Frequency|8000 ps = 125MHz|
|Write Pipe Stages|4|
|Memory Type|Components|
|Memory Part|MT47H32M16-3|
|Data Width|32|
|Data Mask|Uncheck|
|>||
|Burst Length|4|
|Burst Type|sequential|
|Output Drive Strength|Fullstrength|
|RTT(nominal)-ODT|75ohms ?|
|DQS# Enable|Enable|
|>||
|Use DCM|Uncheck|
|Class for Address and Control|Class II|
|Class for Data|Class II|
|Debug Signals for Memory Controller|Disable|

- (2010/06/01追記) DQS# Enable は Disable にしないと MAP でこけることが分かりました。

** Available/Reserved ピンは指定しない [#c95111af]

つぎにピン配置を決めるのですが・・・

[Create Design] モードというのは、新たにＰＣＢを起こす際に
MIG にお勧めの結線方法を提案してもらうというモードなので、
このモードではどんなに頑張っても１つ１つのピン配置を
こちらから指定することはできません。

メモリとの接続に使ってもよいピンを MIG に教えると、
MIG がピン配置を勝手に決め、その配置でコアを生成するという
話になっています。

デフォルトでは全てのピンが Available Pins に入っていて、
MIG はその中から適当なピンを選んでコアを生成します。

もちろんそれでは困るのですが、
どうしようもないので後で直すことにして、
ここではそのままにしておきます。

ちなみに、このページの [Read UCF File] は興味を引くボタンなのですが、、、

他の用途に使っているためにメモリとの配線に使えないピンを Reserved Pins 
として登録するためのもので、メモリとの配線方法を指定するためのものでは無いので、
残念ながら押しても役に立ちません。

** Bank は(念のため)本来のピン配置と同じものを選んでおく [#d099ae7e]

MIG は上述の Available Pins から適当なピンを選んで信号線を割り当てますが、
このページでは信号線の種類毎に、使う Bank を指定することができます。

&attachref(mig4.png,,50%);

目的のボードに合わせてバンクを選択すればよいのだと思います。

** コアを生成する [#m28d5b83]

どんどんページをめくって、最後にライセンスを承諾するとコアが生成されます。

** ピンを指定するための ucf ファイルを作る [#j3b09d33]

ここからいよいよピン配置を指定する段階です。

私の場合 ddr2mi という名前でコアを作ったので、
できたコアは以下のディレクトリにありました。

(project folder)/ipcore_dir/ddr2mi/user_design

このフォルダの par/ddr2mi.ucf に、MIG が適当に決定したピン配置と、
そのピン配置に最適化された回路を生成するための ucf ファイルが作成されています。

このファイルから #bank というコメントが付いている行を抜き出すと、
ピン配置を指定している行だけを抽出できます。

unix ライクなコンソールが使えれば、

 LANG:console
 $ grep -i "#bank" ipcore_dir/ddr2mi/user_design/par/ddr2mi.ucf | sort > ddr2mi_pins.ucf

とすることで、

ddr2mi_pins.ucf
 NET "cntrl0_ddr2_a[0]" LOC = "J21" ;     #bank 1
 NET "cntrl0_ddr2_a[10]" LOC = "B2" ;     #bank 3
 NET "cntrl0_ddr2_a[11]" LOC = "H7" ;     #bank 3
 NET "cntrl0_ddr2_a[12]" LOC = "G6" ;     #bank 3
 ...
 
 NET "cntrl0_ddr2_dqs_n[6]" LOC = "J4";     #bank 3
 NET "cntrl0_ddr2_dqs_n[7]" LOC = "J6";     #bank 3
 NET "cntrl0_rst_dqs_div_in" LOC = "G4";     #bank 3
 NET "cntrl0_rst_dqs_div_out" LOC = "F5";     #bank 3

のようなファイルができます。

これを自分のボードに合わせて編集し、正しいピンを指定します。

** ucf ファイルを元にコアのピン配置を変更する [#g2034423]

上記の手順でピン配置だけを変更しても、FPGA 内部のプリミティブ配置は MIG 
が最初に提案したピン配置に最適化されているのでそのままでは動きません。

そこで、もう一度 MIG を起動してコアを作り直します。

Design ペインの Hierarchy で先ほど生成した ddr2mi をダブルクリックして MIG を起動します。

&attachref(mig6.png,,50%);

今度は [Verify UCF and Update Design and UCF] を選択し、~
Load Prj File に ipcore_dir/ddr2mi/user_design/mig.prj ~
Load UCF File に ddr2mi_pins.ucf (ピンを指定するための自分で作ったファイル)~
を指定します。

Next を連打して、もう一度ライセンス条項を許諾すると、
指定したピン配置でコアを生成できます。

** 正しいピン配置になっているかどうか確認する [#n22a8f15]

 LANG:console
 $ grep -i "#bank" ipcore_dir/ddr2mi/user_design/par/ddr2mi.ucf | sort > ddr2mi_pins.ucf

としてみると、指定した通りのピン配置でコアが生成されていると思います。


** オリジナルの構成と比べてみる [#qb76bde0]

 LANG:console
 $ grep -i "#bank" ddr2mi_original.ucf | sed -e "s/#bank.*//i" -e "s/\r//" | sort > original-pins.txt
 $ grep -i "#bank" ddr2mi.ucf | sed -e "s/#bank.*//i" -e "s/\r//" | sort > custom-pins.txt
 $ paste *pins.txt > compare.txt

として、形式を整えたものが次の表です。

|ピン名称|カスタム|オリジナル|
|LEFT:|CENTER:|CENTER:|c
|cntrl0_ddr2_a[0]|BGCOLOR(YELLOW):J5|M4|
|cntrl0_ddr2_a[1]|BGCOLOR(YELLOW):M9|M6|
|cntrl0_ddr2_a[2]|BGCOLOR(YELLOW):M10|M5|
|cntrl0_ddr2_a[3]|BGCOLOR(YELLOW):K4|N4|
|cntrl0_ddr2_a[4]|BGCOLOR(YELLOW):K5|N5|
|cntrl0_ddr2_a[5]|BGCOLOR(YELLOW):K2|N2|
|cntrl0_ddr2_a[6]|BGCOLOR(YELLOW):K3|N1|
|cntrl0_ddr2_a[7]|BGCOLOR(YELLOW):L3|N7|
|cntrl0_ddr2_a[8]|BGCOLOR(YELLOW):L4|N6|
|cntrl0_ddr2_a[9]|BGCOLOR(YELLOW):M7|P2|
|cntrl0_ddr2_a[10]|BGCOLOR(YELLOW):M8|P1|
|cntrl0_ddr2_a[11]|BGCOLOR(YELLOW):M3|W6|
|cntrl0_ddr2_a[12]|BGCOLOR(YELLOW):M4|W7|
|cntrl0_ddr2_ba[0]|BGCOLOR(YELLOW):K6|M8|
|cntrl0_ddr2_ba[1]|BGCOLOR(YELLOW):J4|M3|
|cntrl0_ddr2_cas_n|BGCOLOR(YELLOW):L10|K3|
|cntrl0_ddr2_ck[0]|BGCOLOR(YELLOW):N1|AD1|
|cntrl0_ddr2_ck[1]|BGCOLOR(YELLOW):N5|AC2|
|cntrl0_ddr2_ck_n[0]|BGCOLOR(YELLOW):N2|AD2|
|cntrl0_ddr2_ck_n[1]|BGCOLOR(YELLOW):N4|AC3|
|cntrl0_ddr2_cke|BGCOLOR(YELLOW):L7|M7|
|cntrl0_ddr2_cs_n|BGCOLOR(YELLOW):H2|L4|
|cntrl0_ddr2_odt|BGCOLOR(YELLOW):G3|K5|
|cntrl0_ddr2_ras_n|BGCOLOR(YELLOW):H1|L3|
|cntrl0_ddr2_we_n|BGCOLOR(YELLOW):L9|K2|
|reset_in_n|G8|G8|
|cntrl0_ddr2_dq[0]|U9|U9|
|cntrl0_ddr2_dq[1]|V8|V8|
|cntrl0_ddr2_dq[2]|AB1|AB1|
|cntrl0_ddr2_dq[3]|AC1|AC1|
|cntrl0_ddr2_dq[4]|Y5|Y5|
|cntrl0_ddr2_dq[5]|Y6|Y6|
|cntrl0_ddr2_dq[6]|U7|U7|
|cntrl0_ddr2_dq[7]|U8|U8|
|cntrl0_ddr2_dq[8]|AA2|AA2|
|cntrl0_ddr2_dq[9]|AA3|AA3|
|cntrl0_ddr2_dq[10]|Y1|Y1|
|cntrl0_ddr2_dq[11]|Y2|Y2|
|cntrl0_ddr2_dq[12]|T7|T7|
|cntrl0_ddr2_dq[13]|U6|U6|
|cntrl0_ddr2_dq[14]|U5|U5|
|cntrl0_ddr2_dq[15]|V5|V5|
|cntrl0_ddr2_dq[16]|BGCOLOR(YELLOW):R8|V1|
|cntrl0_ddr2_dq[17]|R7|R7|
|cntrl0_ddr2_dq[18]|BGCOLOR(YELLOW):U1|R8|
|cntrl0_ddr2_dq[19]|U2|U2|
|cntrl0_ddr2_dq[20]|P8|P8|
|cntrl0_ddr2_dq[21]|P9|P9|
|cntrl0_ddr2_dq[22]|R5|R5|
|cntrl0_ddr2_dq[23]|R6|R6|
|cntrl0_ddr2_dq[24]|P7|P7|
|cntrl0_ddr2_dq[25]|P6|P6|
|cntrl0_ddr2_dq[26]|T3|T3|
|cntrl0_ddr2_dq[27]|T4|T4|
|cntrl0_ddr2_dq[28]|N9|N9|
|cntrl0_ddr2_dq[29]|BGCOLOR(YELLOW):P10|R2|
|cntrl0_ddr2_dq[30]|P4|P4|
|cntrl0_ddr2_dq[31]|P3|P3|
|cntrl0_ddr2_dqs[0]|V7|V7|
|cntrl0_ddr2_dqs[1]|W3|W3|
|cntrl0_ddr2_dqs[2]|T5|T5|
|cntrl0_ddr2_dqs[3]|R3|R3|
|cntrl0_ddr2_dqs_n[0]|V6|V6|
|cntrl0_ddr2_dqs_n[1]|W4|W4|
|cntrl0_ddr2_dqs_n[2]|U4|U4|
|cntrl0_ddr2_dqs_n[3]|R4|R4|
|cntrl0_rst_dqs_div_in|T9|T9|
|cntrl0_rst_dqs_div_out|T10|T10|

黄色のピンがオリジナルと異なる部分です。

データ部分などはほぼぴったり同じなのですね。

** 気になる点 [#kbec5408]

カスタム .ucf を喰わせた後、Verification Report のところでかなりの数の Warning が出ました。

                       Verification Report                          
 
 /*******************************************************/
 /*                   Controller 0                           
 /*******************************************************/
 Checking pins allocated to Data bits ...
 Checking pins allocated to Strobe bits ... 
 Checking pins allocated to Mask bits ...
 Checking pins allocated to Clock bits ... 
 Checking pins allocated to Address bits ...
 Checking pins allocated to BankAddress bits ...
 WARNING: LUT delay location constraint for dqs_delayed column of dqs[3] are missing..
 WARNING: LUT delay BEL constraint constraints of dqs[3] are missing..
 WARNING: Fifo write address and write enable constraints of dqs[3] are missing..
 WARNING: Slice location constraints of dq[31] are missing..
 WARNING: Slice location constraints of dq[30] are missing..
 WARNING: Slice location constraints of dq[29] are missing..
 WARNING: Slice location constraints of dq[28] are missing..
 WARNING: Slice location constraints of dq[27] are missing..
 WARNING: Slice location constraints of dq[26] are missing..
 WARNING: Slice location constraints of dq[25] are missing..
 WARNING: Slice location constraints of dq[24] are missing..
 WARNING: LUT delay location constraint for dqs_delayed column of dqs[2] are missing..
 WARNING: LUT delay BEL constraint constraints of dqs[2] are missing..
 WARNING: Fifo write address and write enable constraints of dqs[2] are missing..
 WARNING: Slice location constraints of dq[23] are missing..
 WARNING: Slice location constraints of dq[22] are missing..
 WARNING: Slice location constraints of dq[21] are missing..
 WARNING: Slice location constraints of dq[20] are missing..
 WARNING: Slice location constraints of dq[19] are missing..
 WARNING: Slice location constraints of dq[18] are missing..
 WARNING: Slice location constraints of dq[17] are missing..
 WARNING: Slice location constraints of dq[16] are missing..
 WARNING: LUT delay location constraint for dqs_delayed column of dqs[1] are missing..
 WARNING: LUT delay BEL constraint constraints of dqs[1] are missing..
 WARNING: Fifo write address and write enable constraints of dqs[1] are missing..
 WARNING: Slice location constraints of dq[15] are missing..
 WARNING: Slice location constraints of dq[14] are missing..
 WARNING: Slice location constraints of dq[13] are missing..
 WARNING: Slice location constraints of dq[12] are missing..
 WARNING: Slice location constraints of dq[11] are missing..
 WARNING: Slice location constraints of dq[10] are missing..
 WARNING: Slice location constraints of dq[9] are missing..
 WARNING: Slice location constraints of dq[8] are missing..
 WARNING: LUT delay location constraint for dqs_delayed column of dqs[0] are missing..
 WARNING: LUT delay BEL constraint constraints of dqs[0] are missing..
 WARNING: Fifo write address and write enable constraints of dqs[0] are missing..
 WARNING: Slice location constraints of dq[7] are missing..
 WARNING: Slice location constraints of dq[6] are missing..
 WARNING: Slice location constraints of dq[5] are missing..
 WARNING: Slice location constraints of dq[4] are missing..
 WARNING: Slice location constraints of dq[3] are missing..
 WARNING: Slice location constraints of dq[2] are missing..
 WARNING: Slice location constraints of dq[1] are missing..
 WARNING: Slice location constraints of dq[0] are missing..
 WARNING: Some of the RLOC/U_SET Constraints of the LUT delay calibration circuit are missing.
 WARNING: Some of the BEL constraints of the LUT delay calibration circuit are missing.
 WARNING: Slice location constraint for delayed rst_dqs_div_out signal is missing.
 
 Verification completed. Found the following warnings.
 Number of warnings in the input UCF = 47.
 Verification Successful.
 All signals in the UCF were allocated correctly.

与えた .ucf ファイルにはピン配置制約以外書いていないので、それを検出しているものであって、
できあがった .ucf ファイルはこれら Warning の点を修正したものであると考えていたのですが、
試しに再生成された .ucf ファイルを指定して Verify UCF and Update Design and UCF してみたところ、、、

                       Verification Report                          
 
 /*******************************************************/
 /*                   Controller 0                           
 /*******************************************************/
 Checking pins allocated to Data bits ...
 Checking pins allocated to Strobe bits ... 
 Checking pins allocated to Clock bits ... 
 Checking pins allocated to Address bits ...
 Checking pins allocated to BankAddress bits ...
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five-slice_x3y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four-slice_x2y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one-slice_x2y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six-slice_x3y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three-slice_x2y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two-slice_x2y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five-slice_x1y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four-slice_x0y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one-slice_x0y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six-slice_x1y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three-slice_x0y78" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two-slice_x0y79" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four-f" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one-f" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four-f" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one-f" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two-g" for dqs_delayed column of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit0-slice_x1y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit1-slice_x1y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit2-slice_x1y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit3-slice_x1y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit0-slice_x3y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit1-slice_x3y74" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit2-slice_x3y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit3-slice_x3y75" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[3].fifo_0_wr_en_inst-slice_x1y77" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[3].fifo_1_wr_en_inst-slice_x3y77" for Fifo write address or write enable of dqs[3] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit7-slice_x2y86" allocated for dq[31] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit7-slice_x2y87" allocated for dq[31] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit6-slice_x0y86" allocated for dq[30] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit6-slice_x0y87" allocated for dq[30] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit5-slice_x2y84" allocated for dq[29] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit5-slice_x2y85" allocated for dq[29] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit4-slice_x0y84" allocated for dq[28] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit4-slice_x0y85" allocated for dq[28] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit3-slice_x2y76" allocated for dq[27] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit3-slice_x2y77" allocated for dq[27] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit2-slice_x0y76" allocated for dq[26] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit2-slice_x0y77" allocated for dq[26] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit1-slice_x2y74" allocated for dq[25] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit1-slice_x2y75" allocated for dq[25] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit0-slice_x0y74" allocated for dq[24] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit0-slice_x0y75" allocated for dq[24] is invalid.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five-slice_x3y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four-slice_x2y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one-slice_x2y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six-slice_x3y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three-slice_x2y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two-slice_x2y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five-slice_x1y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four-slice_x0y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one-slice_x0y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six-slice_x1y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three-slice_x0y66" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two-slice_x0y67" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four-f" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one-f" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four-f" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one-f" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two-g" for dqs_delayed column of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit0-slice_x1y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit1-slice_x1y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit2-slice_x1y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit3-slice_x1y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit0-slice_x3y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit1-slice_x3y62" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit2-slice_x3y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit3-slice_x3y63" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[2].fifo_0_wr_en_inst-slice_x1y65" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[2].fifo_1_wr_en_inst-slice_x3y65" for Fifo write address or write enable of dqs[2] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit7-slice_x2y70" allocated for dq[23] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit7-slice_x2y71" allocated for dq[23] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit6-slice_x0y70" allocated for dq[22] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit6-slice_x0y71" allocated for dq[22] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit5-slice_x2y68" allocated for dq[21] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit5-slice_x2y69" allocated for dq[21] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit4-slice_x0y68" allocated for dq[20] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit4-slice_x0y69" allocated for dq[20] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit3-slice_x2y60" allocated for dq[19] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit3-slice_x2y61" allocated for dq[19] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit2-slice_x0y60" allocated for dq[18] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit2-slice_x0y61" allocated for dq[18] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit1-slice_x2y58" allocated for dq[17] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit1-slice_x2y59" allocated for dq[17] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit0-slice_x0y58" allocated for dq[16] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit0-slice_x0y59" allocated for dq[16] is invalid.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-slice_x3y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-slice_x2y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-slice_x2y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-slice_x3y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-slice_x2y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-slice_x2y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-slice_x1y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-slice_x0y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-slice_x0y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-slice_x1y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-slice_x0y44" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-slice_x0y45" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0-slice_x1y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1-slice_x1y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2-slice_x1y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3-slice_x1y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0-slice_x3y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1-slice_x3y40" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2-slice_x3y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3-slice_x3y41" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst-slice_x1y43" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst-slice_x3y43" for Fifo write address or write enable of dqs[1] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7-slice_x2y50" allocated for dq[15] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7-slice_x2y51" allocated for dq[15] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6-slice_x0y50" allocated for dq[14] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6-slice_x0y51" allocated for dq[14] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5-slice_x2y46" allocated for dq[13] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5-slice_x2y47" allocated for dq[13] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4-slice_x0y46" allocated for dq[12] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4-slice_x0y47" allocated for dq[12] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3-slice_x2y42" allocated for dq[11] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3-slice_x2y43" allocated for dq[11] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2-slice_x0y42" allocated for dq[10] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2-slice_x0y43" allocated for dq[10] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1-slice_x2y38" allocated for dq[9] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1-slice_x2y39" allocated for dq[9] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0-slice_x0y38" allocated for dq[8] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0-slice_x0y39" allocated for dq[8] is invalid.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-slice_x3y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-slice_x2y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-slice_x2y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-slice_x3y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-slice_x2y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-slice_x2y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-slice_x1y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-slice_x0y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-slice_x0y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-slice_x1y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-slice_x0y30" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-slice_x0y31" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0-slice_x1y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1-slice_x1y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2-slice_x1y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3-slice_x1y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0-slice_x3y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1-slice_x3y26" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2-slice_x3y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3-slice_x3y27" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst-slice_x1y29" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst-slice_x3y29" for Fifo write address or write enable of dqs[0] is invalid or missing.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7-slice_x2y36" allocated for dq[7] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7-slice_x2y37" allocated for dq[7] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6-slice_x0y36" allocated for dq[6] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6-slice_x0y37" allocated for dq[6] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5-slice_x2y34" allocated for dq[5] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5-slice_x2y35" allocated for dq[5] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4-slice_x0y34" allocated for dq[4] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4-slice_x0y35" allocated for dq[4] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3-slice_x2y28" allocated for dq[3] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3-slice_x2y29" allocated for dq[3] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2-slice_x0y28" allocated for dq[2] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2-slice_x0y29" allocated for dq[2] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1-slice_x2y26" allocated for dq[1] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1-slice_x2y27" allocated for dq[1] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0-slice_x0y26" allocated for dq[0] is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0-slice_x0y27" allocated for dq[0] is invalid.
 WARNING: The signal cntrl0_led_error_output1 is missing or allocated to invalid I/O.
 WARNING: The signal cntrl0_data_valid_out is missing or allocated to invalid I/O.
 WARNING: The signal cntrl0_init_done is missing or allocated to invalid I/O.
 WARNING: Slice location constraint for delayed rst_dqs_div_out signal is not correct.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-slice_x1y52" for delayed rst_dqs_div_in signal is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-slice_x1y52" for delayed rst_dqs_div_in signal is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-slice_x0y53" for delayed rst_dqs_div_in signal is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-slice_x1y53" for delayed rst_dqs_div_in signal is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-slice_x0y53" for delayed rst_dqs_div_in signal is invalid.
 WARNING: Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-slice_x0y52" for delayed rst_dqs_div_in signal is invalid.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-g" for delayed rst_dqs_div_in signal is not correct.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-f" for delayed rst_dqs_div_in signal is not correct.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-f" for delayed rst_dqs_div_in signal is not correct.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-g" for delayed rst_dqs_div_in signal is not correct.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-g" for delayed rst_dqs_div_in signal is not correct.
 WARNING: BEL constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-g" for delayed rst_dqs_div_in signal is not correct.
 
 Verification completed. Found the following warnings.
 Number of warnings in the input UCF = 216.
 Verification Successful.
 All signals in the UCF were allocated correctly.

むしろ WARNING が大幅に増えていました（泣

対照的に、ピン配置を指定せず、Create Design で作った .ucf ファイルをそのまま指定して
Verify UCF and Update Design and UCF すると、以下のように Warning は１つも出ません。

                       Verification Report                          
 
 Reading design libraries of xc3sd1800a-fg676... successful !
 
 /*******************************************************/
 /*                   Controller 0                           
 /*******************************************************/
 Checking pins allocated to Data bits ...
 Checking pins allocated to Strobe bits ... 
 Checking pins allocated to Clock bits ... 
 Checking pins allocated to Address bits ...
 Checking pins allocated to BankAddress bits ...
 Verification Successful.
 All signals in the UCF were allocated correctly.

** うまくいってない！ [#g0fbe241]

ここまでやっておいて何ですが、上記手順ではうまく .ucf を再生成できていないようです。

** うまく行きました [#r96d179f]

で、ものは試し、と、上記のように大量の Warning が出たのをめげずに
進んで、もう一度コアを作り直し、そうしてできた .ucf ファイルを
Verify UCF and Update Design and UCF に与えたところ、

                       Verification Report                          
 
 /*******************************************************/
 /*                   Controller 0                           
 /*******************************************************/
 Checking pins allocated to Data bits ...
 Checking pins allocated to Strobe bits ... 
 Checking pins allocated to Clock bits ... 
 Checking pins allocated to Address bits ...
 Checking pins allocated to BankAddress bits ...
 Verification Successful.
 All signals in the UCF were allocated correctly.

のように、WARNING が出なくなりました。

もともと、「ピン配置だけを抜き出して書き換えた」 .ucf ファイルを作ったのが間違いで、
オリジナルの .ucf ファイルを「ピン配置部分だけを書き換えた」.ucf ファイルを与えて 
Verify UCF and Update Design and UCF すれば良かったのかもしれません。

とりあえず、これで先に進めます。

** MAP でエラー [#lacd5291]

上記設定で作ったコアを組み込んでプロジェクトをコンパイルしたら、
MAP 段階で以下のエラーが出ました。

 ERROR:PhysDesignRules:760 - Incompatible programming for IO standard. IO
    standard LVDS_25 of comp ddr2_dqs<0> does not allow both input and output
    programming on the same comp.
 ERROR:PhysDesignRules:760 - Incompatible programming for IO standard. IO
    standard LVDS_25 of comp ddr2_dqs<1> does not allow both input and output
    programming on the same comp.
 ERROR:PhysDesignRules:760 - Incompatible programming for IO standard. IO
    standard LVDS_25 of comp ddr2_dqs<2> does not allow both input and output
    programming on the same comp.
 ERROR:PhysDesignRules:760 - Incompatible programming for IO standard. IO
    standard LVDS_25 of comp ddr2_dqs<3> does not allow both input and output
    programming on the same comp.
 ERROR:Pack:1642 - Errors in physical DRC.

そもそも .ucf には
 NET  "cntrl0_ddr2_dqs[*]"                       IOSTANDARD = DIFF_SSTL18_II;
 NET  "cntrl0_ddr2_dqs_n[*]"                     IOSTANDARD = DIFF_SSTL18_II;

と書かれているので、なぜ上記エラーが出るのかまったく不明なのですが・・・

http://forums.xilinx.com/t5/Old-ISE-Board-no-new-thread/Error-compilation-with-MIG-DDR2-Spartan-3an/m-p/13532 によれば MIG のオプションで DQS# enable --> disable(1) の変更が必要だそうです？

仕方がないので、これを試すことにしました。

で、もう一度始めから Create Design するのは面倒だったので、
.prj ファイルのパラメータを変更して Verify UCF and Update Design and UCF してみたところ、
ちゃんと Summary 画面で
 DQS# Enable : Disable(1)

となっていました。

その次の画面で

 ERROR: Differential dqs[3] is disabled in MIG project file but the pin out is found in UCF
 ERROR: Differential dqs[2] is disabled in MIG project file but the pin out is found in UCF
 ERROR: Differential dqs[1] is disabled in MIG project file but the pin out is found in UCF
 ERROR: Differential dqs[0] is disabled in MIG project file but the pin out is found in UCF

なるエラーが出たので、.ucf ファイルから

 NET "cntrl0_ddr2_dqs_n[0]"

などの行をすべて削除してもう一度読み込ませたところ、

                       Verification Report                          
 
 Reading design libraries of xc3sd1800a-fg676... successful !
 
 /*******************************************************/
 /*                   Controller 0                           
 /*******************************************************/
 Checking pins allocated to Data bits ...
 Checking pins allocated to Strobe bits ... 
 Checking pins allocated to Clock bits ... 
 Checking pins allocated to Address bits ...
 Checking pins allocated to BankAddress bits ...
 Verification Successful.
 All signals in the UCF were allocated correctly.

として、正しくコアを生成できました。

生成されたコアからは cntrl0_ddr2_dqs_n というピンが無くなっていました。

これで MAP は通るようになりました。

** 次は PAR でエラー [#dabcd115]

MAP は通ったものの、次は PAR でエラーです。

Post-MAP Static Timing では All constraints were met. 
となっているにもかかわらず、次のエラーが出てしまいます。

 ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays 
   alone exceed the constraint. A timing constraint summary below shows the failing constraints 
   (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) 
   with the Mapped NCD and PCF files to identify which constraints and paths are failing because 
   of the component delays alone. If the failing path(s) is mapped to Xilinx components as
   expected, consider relaxing the constraint. If it is not mapped to components as expected, 
   re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass 
   this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. 
 
   For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference 
   manual; for more information on TRCE, consult the Xilinx Command Line Tools User Guide "TRACE" 
   chapter.

その後のメッセージから特定される箇所は、

|  Constraint                                |    Check    | Worst Case Slack |  Best Case Achievable  | Timing Errors  |   Timing Score   |
|* TS_clock_gen_clk_125MHz90_pre = PERIOD TIMEGRP "clock_gen_clk_125MHz90_pre" TS_clk_125MHz_in PHASE 2 ns HIGH 50% | SETUP       |    -0.926ns|    11.704ns|      4|        2202|
|~| HOLD        |     0.399ns|            |       0|           0|

で、これはちょうど MI コアとのインタフェース部分のクロックなのですが、
Post-MAP Static Timing では周期の 8ns に対して setup path は 3.389 と表示されており、
当然エラーにはならないはずなのです。

これでは何が悪いのか分からないので困ってしまうのですが・・・

メッセージを参考に、XIL_TIMING_ALLOW_IMPOSSIBLE という環境変数に 1 
を設定して再度トライしたところ、数多く出力されるメッセージの中に

 WARNING:Place:414 - The input design contains local clock signal(s). To get a better result,
 we recommend users run map with the "-timing" option set before starting the placement.

というのがありました。

MIG の生成するコアは negedge clk0 に同期した信号を要求するので、
そのために local clock signals が使われているとのメッセージが出ているのだと思います。

そして、このせいで Post-MAP Static Timing で正しい見積もりが出せなかったということでしょうか。

実際 XIL_TIMING_ALLOW_IMPOSSIBLE で無理矢理通した後の、
Post-PAR Static Timing を見ても、それらしいエラーが出ていません（困

そこで、Map の Process Properties の Other Map Command Line Options に 
~-timing を記入してトライしたところ、Phase 4.2  Initial Clock and IO Placement で
ものすっごく時間が掛かるようになりました。

というか・・・ＣＰＵを１００％使い切ったまま１０分以上返ってこないです？！

** negedge clk0 を posedge clk180 で書き直す [#j3e6a084]

negedge clk0 のクロックドメインは後述するステートマシン部だけなので、
それほど大きなドメインではないのですが、local というには大きくて、
それが MAP に負担が掛かっている、ということでしょうか。

これらの信号を生成するためにもう１つクロック線を使って、
ユーザーコード側で negedge clk0 が必要な部分を、
180 度位相の異なる clk180 の posedge で動かすことにしました。

うーん、まだだめですね。Phase 4.2 から戻ってきません。
~-timing オプションを付けると map が終了しないのは、回避の仕方が分かりません。

~-timing オプションを取ってみたところ、新たに PAR でエラーが出て、
たぶん BUFG が足りないと言うことのようです。

 ERROR:Place:962 - A DCM / BUFGCTRL clock component pair have been found that are not placed at an optimal DCM / BUFGCTRL
   site pair. The DCM component <clock_gen/DCM_SP_inst> is locked to site <DCM_X1Y3> and the corresponding BUFGCTRL
   component <clock_gen/clk_125MHz90_bufg> is locked to site <BUFGMUX_X1Y1>. This will not allow the usage of the fast
   path between the DCM and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
   < PIN "clock_gen/DCM_SP_inst.CLK90" CLOCK_DEDICATED_ROUTE = FALSE; >

ゴールは遠い感じです。

** 気になるメッセージ [#v9396154]

PAR 時にいくつか気になるメッセージが出ていたので、
実際には後で対処するとして、忘れないようとりあえずここにメモしておきます。

 INFO:Place:834 - Only a subset of IOs are locked. Out of 97 IOs, 39 are locked and 58 are not 
 locked. If you would like to print the names of these IOs, please set the environment variable 
 XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 

メモリと接続されるピン配置が合ってません。
もしかして、MIG の生成した .ucf がまったく効いていない？

何か根本的な手順が抜けているのかもしれません・・・

ただ、MIG の生成した .ucf ファイルを指定して明示的にプロジェクトに追加しようとすると
すでにプロジェクトに含まれるため追加できない旨のエラーメッセージが出るので、
入っていない訳じゃないみたいなんですが・・・

 WARNING:Place:619 - This design is using a Side-BUFG site due to placement constraints on a BUFG, 
 DCM, clock IOB or the loads of these components. It is recommended that Top and Bottom BUFG sites 
 be used instead of Side-BUFG sites whenever possible because they can reach every clock region on 
 the device. Side-BUFG sites can reach only clock regions on the same side of the device and also 
 preclude the use of certain Top and Bottom BUFGs in the same clock region.

これも要チェック。

* MIG が生成したコアを使って Spartan 3A DSP から DDR2 メモリにアクセスする [#p0f9bc5f]

まだ準備段階です。

Spartan 3A DSP 1800 Starter Platform には Micron の 16bit 幅で 512Mbit の 
DDR2 SDRAM である [[MT47H32M16BM-3>http://www.micron.com//document_download/?documentId=455]] が
２つ載っていて、合計で 32bit 幅 1024Mbit の構成になっています。

DDR2 メモリには最低動作周波数が規定されていて、このチップでは 125MHz となっているため、
Spartan 3 ではちょっと厳しめですが、この周波数でデータの受け渡しをしなければなりません。

また、MIG のインターフェースは元クロックと 90度 および 180度 
位相の異なるクロックを利用してデータの受け渡しをするように設計されていて、
そのあたりもちょっとハードルが高いです。

とはいえ、考え方が分かってしまえば、高速回路設計の勉強にもなっていい感じです。

（まだ実機で動かせるところまで進んでいませんが）

** メモリの構成 [#i33d0468]

合計 1024Mbit で 32bit 幅なので、アドレス空間は 0x0000000 - 0x1ffffff の 25ビット幅になります。

ddr2mi_parameter_0.v を見ると
 LANG:verilog
 `define   ROW_ADDRESS                              13
 `define   COLUMN_ADDRESS                           10
 `define   BANK_ADDRESS                             2

となっていて、合計値は正しく 25 ビットになっていました。

** モードレジスタの値 [#w267ac5a]

ddr2mi_parameter_0.v によれば、
 LOAD_MODE_REGISTER                       13'b0010100110010

となっていますので、これをメモリのデータシートと突き合わせると、

&attachref(mode_reg.png);

|項目|値|意味|
|Mode Register Definition|00 | Mode register (MR)|
|PD Mode|0| Fast exit|
|Write Recovery|010 | 3|
|DLL Reset|1 | Yes|
|Test Mode|0 | Normal Mode|
|CAS#|0||
|CAS Latency (CL)|11 | 3|
|Burst Type|0 | Sequential|
|Burst Length|010 | 4|

という設定であることが分かります。

** 初期化 [#ub9bfa1e]

MI からは
- cntrl0_sys_rst_tb
- cntrl0_sys_rst90_tb
- cntrl0_sys_rst180_tb

の３つのリセット信号が出力されます。

SDRAM の初期化時間を 200us 取らなければならないため、
システムリセット後 200us 以上にわたりこれらの信号は 1 の値を取ります。

これらすべてが 0 に下りたのを確認した後、
negedge clk0 に同期して mi_command に Initialize memory (3'b010) を１クロックだけ送り、
init_done が上がるのを待てば初期化が終了します。

シミュレーション時には MI のコンパイル時に simulation という定数を `define 
しておけばこの 200us (実際には 280us 程度）を待たずに済みます。

ISE から ModelSim を使ってシミュレーションするのであれば、
"Simulate Behavioral Model" などの上で右クリックして、
[Process Properties...] から [Other VLOG Command Line Options] に
"+define+simulation" ("" は除く) を記入しておくのが手軽です。

** 読み書き [#v30db95a]

32bit のメモリにアクセスする場合、MI とは 64bit のデータをやりとりします。

書き込みでは、上位 32bit が先に、下位 32bit が後に、デバイスに送られます。

読み込みでは、先に受信した方を上位に、後に受信した方を下位に詰めて渡されます。

アドレスは clk0 の negedge に同期して、~
データは clk90 の posedge に同期して、~
やりとりされることになっています。

この取り決めに始め戸惑いましたが、よく見てみると難しいことはないようです。

- ステートマシンは negedge clk0 同期で作成する
-- read も write も、アドレスや burst done の出力タイミングは同じでよい
- データを扱う posedge clk90 ドメインは
-- read では data_valid だけ見てデータを取り込めばよい
-- write では cmd_ack が立った次のクロックからデータを書き出せばよい

という単純な話でした。

write の際に、
negedge clk0 で遷移する信号を~
posedge clk90 ドメインで読み取る必要が生じるのですが、~
fifo をうまく使えばそのままで十分にセットアップ時間が取れるため、
普通に書いてしまって大丈夫でした。

ツールが位相違いのクロックをちゃんと認識してセットアップ・ホールド
時間解析をしてくれるのでこういう使い方ができるのですね。

サブクロックの最適化が必要になるような高速回路の設計について、
その片鱗が見えた気がしました。

以上、まだシミュレーション段階でうまく行きそう、という段階なので、
これからが正念場です（汗


* メモ [#s277dbef]

- Invalid property "SYN_USEIOFF 1" というワーニングは XST が Synplify 用の制約である SYN_USEIOFF を認識できないために出るものなので、無視して良さそうです。

* コメント [#h67dcb11]

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