HDL/VivadoでAXIバスを利用 の添付ファイル一覧
更新電気回路/HDL/VivadoでAXIバスを利用
- add-lite-ips.png [詳細]
- add-simulation-source.png [詳細]
- address-assigned.png [詳細]
- assign-address.png [詳細]
- axi-bus-handshake.png [詳細]
- axi-bus-variations.png [詳細]
- axi4-lite-simulated.png [詳細]
- axi4_lite_master_bfm-design.png [詳細]
- axi4_lite_master_bfm-test.png [詳細]
- connect-dma-intout.png [詳細]
- connection-automation.png [詳細]
- create-axi4-peripheral.png [詳細]
- create-design_1_test.png [詳細]
- create-ip-menu.png [詳細]
- create-ip.png [詳細]
- create-smastertest.png [詳細]
- create_block_design.png [詳細]
- design-routed.png [詳細]
- dma-registers-are-accessible.png [詳細]
- generate-block-design.png [詳細]
- layout-regenerated.png [詳細]
- lite-ips-placed.png [詳細]
- lite_slave_config.png [詳細]
- lite_slave_creation.png [詳細]
- lite_slave_project.png [詳細]
- lite_sm_generated.png [詳細]
- main-sv.png [詳細]
- new-project.png [詳細]
- no-ports.png [詳細]
- not_delete_project.png [詳細]
- numbers-of-ports.png [詳細]
- optimize-routing-button.png [詳細]
- project-name.png [詳細]
- project-summary.png [詳細]
- regenerate-layout.png [詳細]
- rtl-project.png [詳細]
- set-as-top.png [詳細]
- smaster-added.png [詳細]
- smaster-address-editor.png [詳細]
- test_lite_slave.png [詳細]
- validation-successful.png [詳細]
- verilog-source-generated.png [詳細]
- zynq-7020.png [詳細]
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